SOLICITATION NOTICE
B -- Board Warpage Analysis - Scientific and Technical Services of Printed Circuit Boards
- Notice Date
- 8/9/2005
- Notice Type
- Solicitation Notice
- NAICS
- 541690
— Other Scientific and Technical Consulting Services
- Contracting Office
- Department of Commerce, National Institute of Standards and Technology (NIST), Acquisition Management Division, 100 Bureau Drive, Building 301, Room B129, Mail Stop 1640, Gaithersburg, MD, 20899-1640
- ZIP Code
- 20899-1640
- Solicitation Number
- Reference-Number-05-812-0622
- Response Due
- 8/25/2005
- Archive Date
- 8/31/2005
- Description
- The National Institute of Standards and Technology (NIST) intends on entering into a sole source procurement with Georgia Tech Research Corporation, Office of Sponsored Programs, Georgia Tech, Atlanta, GA 30332 under the authority of FAR Subsection 13.106-1(b) for follow-on work. In order to perform this work the contractor must meet the following requirements: The Contractor must have a Ph.D. in Mechanical Engineering with specialization in information technology and knowledge based methods; The Contractor must be familiar with the AP210 standard with practical experience with its use in: thermal analysis, design optimization, and component bonding analysis in electronic packaging; Advanced collaborative engineering environments; PCB stackup design; PCB warpage analysis; and Printed Wiring Board (PWB) Warpage Analysis Framework (PWAF). Additionally, the contractor must have worked on at least three separate AP210 based projects and have published at least one article on board warpage using the AP210 standard; have knowledge of constrained objects (COBs), multi representational architectures (MRA) for CAD CAE interoperability, and context-based analysis models (CBAMs); and must be familiar with the prototype board warpage tool developed. The purpose of this work is to examine how other printed circuit board design variations can result in board warpage (regardless of warpage idealization levels). Aspects such as plating sequences, solder mask types, and sequential lamination groups shall be examined and captured from the stackup design and stored into AP210 files. This data shall then be used to model how these aspects can result in board warpage. This is a continuation of work completed in a previous order; it is anticipated that a firm-fixed price purchase order will be awarded. Any interested party may submit, in writing, a detailed capability statement to respond to this requirement. However, a determination by the Government to compete this proposed requirement based on responses to this notice is solely within the discretion of the Government. This notice of intent is not a request for quotes. If no affirmative responses are received by August 25, 2004 by 10:00am local time, the Contracting Officer will proceed with the award to Georgia Tech Research Corporation, Office of Sponsored Programs, Georgia Tech.
- Place of Performance
- Address: Atlanta, GA
- Country: US
- Country: US
- Record
- SN00865898-W 20050811/050809211812 (fbodaily.com)
- Source
-
FedBizOpps.gov Link to This Notice
(may not be valid after Archive Date)
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