59 -- INTEGRATED CIRCUITS

Notice Date

March 1, 2001

Contracting Office

Crane Division, Naval Surface Warfare Center, Code 1164, 300 Highway 361, Crane, In 47522-5001

ZIP Code

47522-5001

Solicitation Number

N00164-01-R-0043

Response Due

March 9, 2001

Point of Contact

Mr. J.D. Martin, Code 1164EF, telephone 812-854-3723, fax 812-854-5666, e-mail martin_j@crane.navy.mil

Description

This is a combined synopsis/solicitation for commercial items prepared in accordance with the format in FAR 12.6, as supplemented with additional information included in this notice. This announcement constitutes the only solicitation; proposals are being requested and a written solicitation will not be issued. Solicitation Number N00164-01-R-0043 is hereby issued as a request for proposal (RFP). Incorporated provisions and clauses are those in effect through Federal Acquisition Circular 97-19 and DCN 20001001. The North American Industry Classification System (NAICS) Code for this procurement is 334413 and the size standard is 500 employees. This requirement will be for the following: CLIN 0001 Quantity of 25 copies of sixteen (16) Circuit Designs in accordance with the specifications stated herein. Note that this buy is being conducted in accordance with FAR 13.5 and is being issued under full and open competitive procedures. Delivery is required FOB Destination to NSWC Crane Division, 300 Highway 361, Crane, IN 47522-5001, Bldg. #2088, within 120 days after award. Early deliveries are acceptable. Final inspection will be at destination NSWC Crane. Selection for award will be based on past performance and price for offers. Past performance and price are of equal importance. Offers that are non-compliant with any material requirement of this solicitation may be rejected without further consideration for award. This requirement is issued as a firm fixed-price contract. This contract will be awarded utilizing Simplified Acquisition Procedures. The contractor shall extend to the Government the full coverage of commercial sale warranty provided such warranty is available at no additional cost to the Government. Offerors shall include a copy of their warranty with the offer. Clauses/provisions: 52.203-3; 52.211-14 (DO Rated Order); 52.211-15; 52.212-1; 52.212-3 Alt l [FILL-IN]; 52.212-4; 52-212-5 (incorporating 52.219-4; 52.219-8; 52.222-21; 52.222-26; 52.222-35; 52.222-36; 52.222-37; 52.225-16; 52.232-33;); 52.215-05 (812-854-3465 fax #); 52-217-5; 252.204-7004; 252.212-7001 (incorporating 252.225-7001; 252.243-7002; 252.247-7023). The offeror shall provide its Commercial and Government Entity (CAGE) Code, Tax Identification Number (TIN), and DUNS number. To be eligible for award you must be properly registered in the Government's Central Contractor Registration (CCR). Offerors may obtain information on CCR registration and annual confirmation requirements by calling 1-888-227-2423, or via the internet @ http://ccr.dlsc.dla.mil or http://www.ccr2000.com. If a change occurs in this requirement, only those offerors that respond to this announcement within the required time frame will be provided any changes/amendments and considered for future discussions and/or award. All responsible sources may submit an offer, which will be considered by the agency. Offers may be faxed or e-mailed to Mr. J.D. Martin at FAX 812-854-3465, e-mail address martin_j@crane.navy.mil. All required information must be received on or before 09 March 2001 @ 2:00 PM Eastern Standard Time. Our mission is to provide quality and responsive acquisition services for this Command. In an effort to continue to improve our services, we are conducting a survey of our vendors. This survey may be found on the World Wide Web at the following address: http://www.crane.navy.mil/supply/VendorSurvey.htm. Your comments will help us determine if we are accomplishing this and show us ways to improve our processes. Please consider taking the time to complete the survey. Specification requirements are as follows: 1. Scope: NAVSEA Crane is leading a team investigating single event transients (SET) in digital CMOS circuits generated by ionizing particles (e.g. protons, cosmic rays and neutrons) found in both the space and upper atmosphere environments. For this investigation, a set of eight test circuits have been designed, which must be fabricated in both 0.25 micron and 0.18 micron CMOS to investigate the effects of technology scaling, and the effectiveness of proposed protection techniques in scaled CMOS technology. As these are test chips, not production devices, only 25 of each of the 16 circuit types is required. The only practical way to obtain such limited quantities of multiple designs in state-of-the-art CMOS technology is through a multi-project fabrication process. The purpose of this document is to procure a quantity of 25 each of the set of 16 test chips in the two CMOS technologies and have part of them packaged in ceramic packages suitable for test in an accelerator. 2. Semiconductor Process: To meet all requirements of the investigation, the two processes selected are the TSMC 0.25 micron CMOS process (capable of operating with 2.5/3.3 volt supply voltage) and the TSMC 0.18 micron CMOS process (capable of operating with 1.8/3.3 volt supply voltage). Each technology shall be capable of supporting five levels of metallization, one layer of polysilicon (silicide), be blockable and allow stacked vias. The eight unique designs (to be supplied by the government) have been targeted for these two processes, utilizing design rules totally compatible with scalable CMOS circuit design rules. The government would incur significant expense to revise the designs for a different process. The designs to be submitted will pass all design rule checks required for incorporation into the next available fabrication run. The files will be provided in electronic format in GDS-II format. The eight designs in each technology will be submitted as a unit to allow fabrication on a single process run. Bonding diagrams for each of the device types shall be provided at the time the design tapes are submitted. 3. TSMC 0.25 micron Chip Set: The eight chips to be fabricated in TSMC 0.25 micron CMOS technology consist of two small designs and six large designs, as described in 3a and 3b. 3a. Small circuits: Two designs share a common bond pad layout of 58 pads, and the physical size of 3017 micron width by 2207 micron length. These chip designs are named SNFNC25 and SDFHC25. Ten of the die shall be packaged in a 84 pin pin-grid array (PGA) ceramic package. The die cavity must face away from the pin mount axis (i.e. up when mounted in a socket) to allow direct impingement of ions from an accelerator on the die surface. The lids shall be attached with tape, and not sealed, for test purposes. The remaining 15 die shall be delivered in die form in a standard waffle pack. 3b. Large circuits: Six designs share a common bond pad layout of 70 pads and the physical size of 3017 micron width by 4475 micron length. These chip designs are named ST3T25, SDYMT25, SDY3T25, SDI3T25, SSCRT25, SSET25. Ten of the die shall be packaged in a 84 pin pin-grid array (PGA) ceramic package. The die cavity must face away from the pin mount axis (i.e. up when mounted in a socket) to allow direct impingement of ions from an accelerator on the die surface. The lids shall be attached with tape, and not sealed, for test purposes. The remaining 15 die shall be delivered in die form in a standard waffle pack. 4. TSMC 0.18 micron Chip Set: The eight chips to be fabricated in TSMC 0.18 micron CMOS technology consist of two small designs and six large designs, as described in 4a and 4b. 4a. Small circuits: Two designs share a common bond pad layout of 58 pads, and the physical size of 3017 micron width by 2207 micron length. These chip designs are named SNFNC18 and SDFHC18. Ten of the die shall be packaged in a 84 pin pin-grid array (PGA) ceramic package. The die cavity must face away from the pin mount axis (i.e. up when mounted in a socket) to allow direct impingement of ions from an accelerator on the die surface. The lids shall be attached with tape, and not sealed, for test purposes. The remaining 15 die shall be delivered in die form in a standard waffle pack. 4b. Large circuits: Six designs share a common bond pad layout of 70 pads and the physical size of 3017 micron width by 4475 micron length. These chip designs are named ST3T18, SDYMT18, SDY3T18, SDI3T18, SSCRT18, and SSET18. Ten of the die shall be packaged in a 84 pin pin-grid array (PGA) ceramic package. The die cavity must face away from the pin mount axis (i.e. up when mounted in a socket) to allow direct impingement of ions from an accelerator on the die surface. The lids shall be attached with tape, and not sealed, for test purposes. The remaining 15 die shall be delivered in die form in a standard waffle pack.

Web Link

Naval Surface Warfare Center, Crane Division's web address (www.crane.navy.mil/supply/announce.htm)

Record

Loren Data Corp. 20010302/59SOL006.HTM (W-059 SN50E866)